In designing a conventional tri-gate panel, the design of a high pin count is commonly adopted at a source side in order to save costs. For example, only one set of fanout terminals and one integrated circuit (IC) chip can be used at the source side. However, a fanout area thus designed generally has a large resistance difference (Rmax−Rmin) therein.
In practice, the major problem caused by a large impedance difference in the fanout area at the source side is color shifting at two sides of the panel during display of a blending picture. With respect to display of a blending picture, a data line would continuously charge two sub-pixels of a pixel before charging two sub-pixels of a next pixel. Since large impedance in the fanout area would cause rather sever RC delay of a signal, the charging condition of a first sub-pixel would be worse than that of a second sub-pixel. Especially for the fanout area having the largest wiring impedance, i.e., two sides of the panel, charging differences between sub-pixels would lead to color shifting.
As a result, a tri-gate display panel needs to be designed, in which, color shifting can be eliminated or would not be generated in displaying a blending picture.